Embodiments relate to a method for forming a semiconductor device, and more particularly to a technology in which a gate has a fin structure with an increased channel length. More specifically, particular embodiments relate to a 6F2 saddle fin gate structure with an increased channel region.
Generally, a semiconductor is a material that falls within an intermediate region between a conductor and a nonconductor from among materials affected by electrical conductivity. Although a semiconductor is similar to a nonconductor in a pure state, electrical conductivity of the semiconductor device is increased by impurity implantation or other manipulation. The semiconductor is used to form a semiconductor device such as a transistor through impurity implantation and conductor connection. A device that has various functions simultaneously while being formed of a semiconductor element is referred to as a semiconductor device. A representative example of the semiconductor device is a semiconductor memory device.
A semiconductor memory device includes a plurality of unit cells each having a capacitor and a transistor. The capacitor is used to temporarily store data, and the transistor is used to transfer data between a bit line and the capacitor in response to a control signal (word line). The data transfer occurs using a semiconductor property whereby an electrical conductivity changes depending on environment. The transistor has three regions, i.e., a gate, a source, and a drain. Electric charges are moved between the source and the drain according to a control signal input to the gate of the transistor. The charges between the source and the drain move through a channel region in accordance with the properties and operation of the semiconductor device.
In the case where a general transistor is formed over a semiconductor substrate, a method of forming a gate over the semiconductor substrate and doping impurities into both sides of the gate so as to form a source and a drain has been used. As the data storage capacity of a semiconductor memory device has increased and integration degree has increased, the size of each unit cell must be gradually decreased.
That is, the design rule of the capacitor and the transistor included in the unit cell has been reduced. Thus, as the channel length of a cell transistor is gradually decreased, the short channel effect, Drain Induced Barrier Lowering (DIBL), etc. occur in the general transistor and thus operational reliability is decreased. By maintaining a threshold voltage such that the cell transistor performs a normal operation, it is possible to solve the phenomena generated due to decrease in channel length. In general, as the channel length of the transistor shortens, the concentration of impurities doped into a region in which the channel is formed has been increased.
However, if the concentration of the impurities doped into the channel region is increased while the design rule is reduced to 100 nm or less, the electric field of a Storage Node (SN) junction is increased, thereby deteriorating the refresh characteristics of a semiconductor memory device. In order to solve this problem, a recessed gate and a saddle fin structure gate have been developed to physically increase a channel length.
Specifically, although a horizontal channel width of the saddle fin structure transistor is short, a vertical channel length thereof can be guaranteed so that doping concentration can be decreased, and refresh characteristics are prevented from being deteriorated.
However, a fin width of the saddle fin structure transistor is extremely reduced due to size reduction of a very small-sized cell of 30 nm or less, so that the effect of channel increase is unavoidably deteriorated.